Velocity SIMD CPU Runtime (Runtime + Scalar x2) #1055
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…y generated parameter instances to Velocity kernels.
…d transfer scalar arguments into the vector world.
…ering of blocks in the schedule.
…the scalar Velocity code generator.
…velocity accelerators.
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@MoFtZ I addressed an issue in the |
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This PR adds the announced SIMD-based CPU runtime fully implemented in managed code. The new
Velocityaccelerator supports most GPU kernels (except those using dynamic shared memory) and is able to utilize SIMD hardware acceleration on modern CPUs, allowing you to run your ILGPU kernels efficiently on then CPU by leveraging the implemented automatic vectorization engine.It supports the following hardware configurations after merging ALL velocity PRs.
128bit-basedX64 SSEandARM64 Neoninstructions (also supportsM1Macs - Mac M Series Support #769, in progress)256bit-basedX64 AVXinstructions (in progress)512bit-basedX64 AVX2instructions (limited feature set; some functions will fallback to256bitregisters)Please note that this is the initial PR adding support for building and managing
Velocitydevices. Furthermore, it also contains the fully-featured code generator to create SIMD-based instructions out of ILGPU IR nodes. However, it does not contain any SIMD code-generation plugins for the backend code generator that will be added later on.This PR integrates CI-support contributed by @MoFtZ in #1096.
Note that this PR is a new version of PR #891.
This PR depends on #1059, #1061, #1062, #1063, #1064, #1065, #1066, #1067, #1068, #1069, #1070, #1071, #1072, #1073, #1074, #1079, and #1081Co-authored-by: MoFtZ [email protected]